The invention relates to a field effect transistor. In particular, it relates to a depletion type n-channel MOS field effect transistor that is used in a circuit to protect against electrostatic breakdown of a magnetic head.
For example, in the case of a magnetic head, such as a GMR magnetic head, incorporated into a magnetic recording device such as an HDD (hard disk drive), a depletion type n-channel MOS field effect transistor is utilized inside a preamplifier IC as a protective circuit to protect the magnetic head from an electrostatic breakdown.
FIG. 8A is a plan view of a depletion type n-channel MOS field effect transistor according to the prior art. As shown in FIG. 8A, gate electrode 41 is formed in a p-type semiconductor region defined on a semiconductor substrate via a gate insulation film, and n-type source region 40S and drain region 40D are formed at surface parts of the p-type semiconductor region at either side part of gate electrode 41. Furthermore, an n-type channel region is formed on the surface part of the p-type semiconductor region immediately below gate electrode 41 so as to form a depletion type n-channel MOS field effect transistor.
Due to increased speeds and capacities of HDDs, there is a demand for depletion type n-channel field effect transistors with lower on-resistances in order to improve the performance of ESD protection elements at low capacitances. To realize this, reductions in the on-resistance and the drain capacitance are required, and a technique for reducing the on-resistance while keeping the drain capacitance unchanged has been adopted.
FIG. 8B is a plan view of a depletion type n-channel MOS field effect transistor according to the prior art. Two gate electrodes 41a and 41b are formed in a p-type semiconductor region provided on a semiconductor substrate via a gate insulation film; and source region 40Sa, drain region 40D, and source region 40Sb are formed in three respective regions that are separated by the two gate electrodes 41a and 41b on the surface part of the p-type semiconductor region. N-channel regions are formed in the p-type semiconductor regions immediately below the two gate electrodes 41a and 41b so as to form a depletion type n-channel MOS field effect transistor.
As opposed to the field effect transistor with the configuration shown in FIG. 8A, in the case of the field effect transistor with the configuration shown in FIG. 8B, because the gate width is set approximately two times as wide while keeping the drain capacitance unchanged, the on-resistance is reduced to approximately one-half. That is, the drain capacitance per unit gate width is reduced by approximately one-half.
However, in recent years, there is a greater demand for faster driving, and further reduction in the on-resistance and the drain capacitance is needed. The invention was devised in light of the aforementioned situation, and its objective is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced further.